(6) If 1Mbyte is the board memory of a graphics card then the mode, which does not support card, is
On a 14” monitor 1600x400 resolution with 16 million colors On a 17” monitor 1600x400 resolution with 256 colors On a 17” monitor 800x400 resolution with 16 million colors On a 14” monitor 800x800 resolution with 256 colors
7.A CPU is connected with a device that is transferring data byte wise, at the rate of10Kbyte/s. Interrupt overhead = 4μs. The byte transfer time between the device interfaces register and CPU or memory is negligible. The minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode is
5 15 25 35
8.A CPU that runs at a frequency of 1GHz has a five-stage pipeline. In the first stage of the pipeline, instructions are fetched. A conditional branch instruction computes the target address and evaluation of the condition is done in the third stage of the pipeline. Until the outcome of the conditional branch is known the process does not fetch the new instruction. In this program out of 109 instructions 20% are instruction of conditional branching. What will be the total execution time of the program is each instruction takes one cycle to complete on average?
1.0s 1.1s 1.2s 1.3s
9.The one that does not interrupt a running process is
Scheduler process Power failure A device Timer
10.3 clock cycles are required for register to/from memory transfer. 1 clock cycle is required for Add with both operands in register and 2 clock cycles per word are required for instruction fetch and decode. What are the total number of clock cycles required to execute the program?
35 28 30 24
On a 14” monitor 1600x400 resolution with 16 million colors On a 17” monitor 1600x400 resolution with 256 colors On a 17” monitor 800x400 resolution with 16 million colors On a 14” monitor 800x800 resolution with 256 colors
7.A CPU is connected with a device that is transferring data byte wise, at the rate of10Kbyte/s. Interrupt overhead = 4μs. The byte transfer time between the device interfaces register and CPU or memory is negligible. The minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode is
5 15 25 35
8.A CPU that runs at a frequency of 1GHz has a five-stage pipeline. In the first stage of the pipeline, instructions are fetched. A conditional branch instruction computes the target address and evaluation of the condition is done in the third stage of the pipeline. Until the outcome of the conditional branch is known the process does not fetch the new instruction. In this program out of 109 instructions 20% are instruction of conditional branching. What will be the total execution time of the program is each instruction takes one cycle to complete on average?
1.0s 1.1s 1.2s 1.3s
9.The one that does not interrupt a running process is
Scheduler process Power failure A device Timer
10.3 clock cycles are required for register to/from memory transfer. 1 clock cycle is required for Add with both operands in register and 2 clock cycles per word are required for instruction fetch and decode. What are the total number of clock cycles required to execute the program?
35 28 30 24