(1) In a computer, whose average memory access time is 20ns has the page fault service time 10Ms. For every 106 memory accesses one page fault is generated. The effective access time for the memory is
10ns 43ns 30ns 25ns
(2) Let T1 be the time taken for a single instruction on a pipelined CPU and T2 be the time take for a single instruction on a non-pipelined but identical CPU. Comparing T1 and T2 we can say that
T1=T2 + the time taken for one instruction fetch cycle T1 T1≤T2 T1≥T2
(3) The number of bits needed for cache indexing is
10 15 5 20
(4) The number of tag bits needed is
17 20 22 25
(5) A and B are the data inputs and Y is the control input of a multiplexer. When Y = 0 data input A is selected and when Y = 1 data input B is selected. The connections required to realize the 2-variable Boolean function f = X+Z, without using any additional hardware are
X to A, 0 to B, Z to Y Z to A, 1 to B, 0 to Y Z to A, 1 to B, X to Y X to A, 1 to B, Z to Y
10ns 43ns 30ns 25ns
(2) Let T1 be the time taken for a single instruction on a pipelined CPU and T2 be the time take for a single instruction on a non-pipelined but identical CPU. Comparing T1 and T2 we can say that
T1=T2 + the time taken for one instruction fetch cycle T1 T1≤T2 T1≥T2
(3) The number of bits needed for cache indexing is
10 15 5 20
(4) The number of tag bits needed is
17 20 22 25
(5) A and B are the data inputs and Y is the control input of a multiplexer. When Y = 0 data input A is selected and when Y = 1 data input B is selected. The connections required to realize the 2-variable Boolean function f = X+Z, without using any additional hardware are
X to A, 0 to B, Z to Y Z to A, 1 to B, 0 to Y Z to A, 1 to B, X to Y X to A, 1 to B, Z to Y
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